SEQUENTIAL PROJECT #4B – D LATCH

 

D LATCH

 

In the standard SR latch, the only way to remember its current state (latch) was to input 00.  But with the Gated SR latch, we can control the circuit to remember its state by setting E to 0. 

 

So there is no longer a need to have the ability to have S and R both as 0 in order to latch since we have E. 

 

This means that we only have two possible states for R and S left since we don’t use R=1 and S=1.  Those two states are R=0 and S=1 (Setting state) and R=1 and S=0 (Resetting state). 

 

Seeing that those two states are opposites, we can replace the two inputs by a single input called D that will be split to the two old R and S locations but will be inverted for one of them.

 

And this also conveniently removes the unwanted case from the SR latch when S=1 and R=1.

 

 

D LATCH FROM SR LATCH BLOCK DIAGRAM

 

 

D LATCH BLOCK DIAGRAM

 

 

REVIEW (D LATCH)

  • A D latch is like an S-R latch with only one input: the “D” input. Activating the D input sets the circuit (like S did in the SR latch), and de-activating the D input resets the circuit (like R did in the SR latch). Of course, this is only if the enable input (E) is activated as well. Otherwise, the output(s) will be latched, unresponsive to the state of the D input.

  • D latches can be used as 1-bit memory circuits, storing either a “high” or a “low” state when disabled, and “reading” new data from the D input when enabled.

 

 

PROJECT EXPECTATIONS

 

You will create a D Latch.  You are encouraged to start by created the gated SR Latch and then adding the NOT gate at the front of it.

 

Show Mr. Campeau your completed D Latch.