SEQUENTIAL PROJECT #4A – GATED SR LATCH THE GATED SR LATCH Sometimes it
is useful to have an on/off signal that controls whether or not a circuit can
change states. It is a way to enable
or disable the circuit. Since the SR
latch is generally always resting at R=0 and S=0 and changes occur only when
R or S get set to one, we can easily add the enable functionality by using
two AND gates. The following
circuit is an SR latch with an Enable line that controls whether the SR latch
is active or not. Note that when
Enable is off, Q and Q1 always stay the same (latch) because the
SR latch is getting two zeros as inputs from the AND gates. GATED SR LATCH BLOCK
DIAGRAM
PROJECT EXPECTATIONS You will
create a Gated SR Latch using an AND chip and a NOR chip. You will have
to demonstrate how your circuit works like a normal SR Latch when E is
1. You will also have to demonstrate
that your circuit’s output state doesn’t change when E is 0. |