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TRUTH TABLE ANALYSIS – SR LATCH TRUTH TABLE ANALYSIS Let’s analyze
the circuit to figure out its truth table. To do this,
it’s useful to have the NOR-gate truth table nearby.
Looking at
the circuit, it’s hard to figure out how to start because we need to know the
values of the outputs to know what is being fed into the inputs. However, we can forget about that for now
by realizing that a NOR gate will always give a 0 if at least one input is
1. So, we can deal with the cases
where we have a 1 as an input. CASE 1: S=1, R=1 Both gates
will have an input of 1 and another unknown input. For a NOR gate, that is
enough for us to know that the output will be 0. So, both Q and Q1 are 0. CASE 2: S=1, R=0 Let’s
consider each gate individually. Bottom gate: If
S is 1, then the output of the lower gate is 0 no matter what the other input
to that gate is. So Q1 is stable at 0
(and is not affected by the other gate’s output). Top gate:
Initially, we only know that R=0 and that the other input will affect the
value of Q (because 00 and 01 give different results for a NOR gate). However, because of the bottom gate’s
output being stable, we know that the second input to the top gate will be
0. Therefore, Q will be 1. Note that this will after to the signal settles after gate propagation delays
for both gates. CASE 3: S=0, R=1 We will start
with the top gate this time because it is the one that is stable. Top
gate: Since its input R is 1, it will
output 0. So Q will be 0. Bottom
gate: Initially, its inputs are S=1
and an unknown value for Q. However,
very shortly the inputs are set, Q is stable at 0 making this gate get inputs
1 and 0. So, Q1 will be 1. CASE 4: S=0, R=0 Unfortunately,
this case is more complicated because there is no guaranteed input that is 1
that forces a known result. In other
words, the values of Q and Q1 will impact the outputs. So lets
consider every possible case here as well. CASE 4A: S=0, R=0, Q=1, Q1=0
(this happens if previous inputs were S=1, R=0) Let’s again
go one gate at a time. Top
gate: The inputs are R=0 and Q1=0.
So the output will be 1. So Q
will continue to be 1 (as long as the input Q1 doesn’t change). Bottom
gate: The inputs are S=0 and Q=1. So
the output will be 0. So Q1 will
continue to be 0 (as long as the input Q doesn’t change). Since both Q
and Q1 are staying the same, the circuit is stable. CASE 4B: S=0, R=0, Q=0, Q1=1
(this happens if previous inputs were S=0, R=1) Using the
same analysis as in the previous case (we can do this because the circuit is
symmetric – identical at top and bottom), we know that Q and Q1
will again stay the same as they were before. CASE 4C: S=0, R=0, Q=0, Q1=0 (to avoid) One might
initially think that this case would happen after the inputs were S=1 and
R=1. However, its practically impossible for both inputs to be switched at
exactly the same time. So rather than
going from S=1 & R=1 directly to S=0 & R=0, we end up with a middle
step such as S=1, R=0 or S=0, R=1 depending on which input was changed
first. If it’s a case where the inputs
we switched together in such a way that we don’t know which was switched
first, then we have an unpredictable result which we want to avoid. However, if
it was possible to switch both at the same time (or perhaps if the circuit
was somehow turned on in this state), then a race condition between the two
gates would start and we would eventually end up with either Q=1 & Q1=0
or the opposite. Unfortunately, again
this result is impossible to predict and hence we want to avoid this
scenario. Note that if
everything was perfect so that we switched both inputs at exactly the same
time and that the propagation delay was exactly the same on both sides of the
circuit, then the values of gate output would constantly change from 0 to 1
to 0 to 1 over and over. But this
doesn’t happen. CASE 4D: S=0, R=0, Q=1, Q1=1 (not
possible) First off,
there is no input combination that would give a 1 for both Q and Q1. So this case isn’t really possible (unless
the circuit was somehow initially turned on in this case). Again, this
case would lead to a race condition between the two gates and we’d end up
with Q=1& Q1=0 or the opposite.
Because it is unpredictable, we’d want to avoid this too. And again, in
a perfect world where timing was perfect, this case would remain unstable and
would see the outputs constantly changing back and forth. THE UNALLOWED STATE Note that the
cases 4C and 4D are the cases where Q and Q1 are the same. In such cases, the next result is
unpredictable. And we like
predictability! So we avoid such
cases. So, to do
this, we generally avoid setting S=1 and R=1 at the same time as it leads to
Q and Q1 being the same. By
disallowing the state S=1, R=1, we can then say a general statement for all
other sub cases of Case 4. If S=0, R=0,
Q not equal to Q1, then the values of Q and Q1 will stay the same. And this
leads to the following truth table:
Note: Latch
means that it remembers its previous state.
It doesn’t change. |
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